Welcome to Logitiles' FPGAcademy!
We provide courses that aim to teach the designers who will participate a design methodology with FPGA with an industrial approach (placing the student colleagues in front of classic design situations that they will find themselves in the company when they are asked to carry out the system design).
Our teaching material is intended for use with our HEXchool board, which will be delivered to students who have purchased participation in the course, included in the price of the course itself. The material will be provided free of charge to students exclusively in electronic format, including the exercise sources, waveforms and bitstreams ready for use.
We suggest you subscribe to our newsletter to be constantly updated on our news, and prepare to become a member of the LOGITILES FPGAcademy, purchasing your first in-person course on digital design with FPGA.
The first two courses that will be available at the beginning of 2026 will be:
- VERILOG Basic (cod. F2.1): An overview of the Verilog language (version 2005) will be provided through extensive use of design examples, highlighting common errors that inexperienced designers make at the outset and demonstrating the results these errors create in synthesis. The tools for successful design will be provided, using verification and validation tools, in preparation for the transition to the SYSTEM VERILOG language, de facto being new version of the Verilog language. EFINIX and AMD design tools will also be used.
In the next few weeks we will announce the course Prices and schedule for multiple participation. For each course we will announce the list of topics and the duration of each one.