The aim of this course is to provide the student with everything needed to know how to design a digital network using the VHDL 2008 language. The main methodologies for describing architectures will be presented, comparing them with regard to the opportunity to synthesize one rather than another, trying to focus on the method of creating RTL structures that by their nature allow for better and simpler project management, in order to the behavior of the various subblocks related to each single edge of the clock. This allows you not to expect many surprises in the synthesis phase and that the symbolic simulation will not have differences compared to the real behavior of the project.
In the next few weeks we will announce the course calendar, the price of each course and any offers for multiple participation. For each course we will announce the list of topics and the duration of each one.